1. Field of the Invention
The present invention relates generally to digital processors and, more particularly, relates to a processor controlled interface between a processor, instruction cache, and main memory.
2. Description of the Relevant Art
A new development in computer architecture has been the introduction of RISC (Reduced Instruction Set Computer) devices, in which, ideally, an instruction is issued each operational cycle. The key to the efficacy of a RISC machine the ability to execute a very large number of instructions each second. Accordingly, much effort is being expended improving the design of these machines to eliminate any delays to instruction processing.
To maintain a high processing rate, instructions need to be accessed from the instruction store at a rate of one per cycle. Special high-speed memory devices are available from which a single instruction may be accessed in one cycle. However, such devices are expensive and are generally used as an instruction cache to store a portion of the instructions in a given program. The remainder of the instructions are stored in main memory.
If the processor references an instruction not stored in the cache, then a "cache miss" occurs. At this point, the processor must stall while the referenced instruction is written to the cache from main memory during a cache refill operation.
Generally, a single instruction can not be accessed from main memory in one cycle. However main memory may include a page mode feature utilized to access one instruction per cycle after an initial set-up time denoted the "memory latency". This latency occurs each time a cache miss occurs and main memory is newly accessed and is a hardware limitation of the memory system.
Most programs are designed so that instructions are accessed from sequential memory locations except in exceptional circumstance, e.g., the occurrence of a branch in the program. Accordingly, if a given reference misses the cache it is likely that the following reference will also miss the cache. Thus, the cache is often refilled with a block of instructions accessed from main memory including the missed instruction so that the subsequent instructions in the block may be sequentially accessed from the cache. Also, if a block of instructions is accessed, the cache may be refilled at a rate of one instruction per cycle after the initial latency.
Unfortunately, the processor must be stalled during a block refill of the cache with the refill latency. i.e., the length of the stall equal to the sum of the main memory latency and the number of words in a block multiplied by the duration of a cycle. Thus the refill latency caused by the block instruction cache refill operation reduces the number of instructions processed each second.
Accordingly, a system for efficiently refilling the cache while not significantly reducing the processing rate is greatly needed in the field.